Tutorial 1 [A modern HDL-based design flow for FPGA prototyping of ASIC's]
The main goal of the workshop is to propose and presents a solution to eliminate the ASIC design verification bottlenecks through innovative hardware application. In addition, authors will introduce new trends of developing ASIC complex designs based on Incremental Prototyping technology. This presentation will acquaint all workshop participants with the most recent and modern EDA solutions, like: BDE Editor, CBS software simulation accelerator, fully customized and integrated synthesis and implementation flows, etc. The main workshop objective is the practical application of new technology used to accelerate simulation of huge HDL designs. This is a hardware embedded simulator board enables designers to perform: hardware accelerated simulation and/or hardware-software co-simulation.

Workshop presentation schedule:
13.04.2003 – DDECS’2003, Poznań (Poland),
17.05.2003 – WRTP’03, Łagów (Poland)

Table of contents:
Tutorial
A modern HDL-based design flow for FPGA prototyping of ASIC’s
  1. Introduction. Purpose.
  2. A modern ASIC design flow conception based on hardware accelerated simulation.
    1. General data flow overview.
    2. The hardware simulation technology overview.
  3. HDL design (VHDL, Verilog).
    1. The design entry tools as a different design hierarchical view conception.
    2. Preparing a hierarchical HDL project.
    3. Automatic test bench generation as simply way to minimize project time verification.
    4. Increasing simulation flexibility using PLI procedures.
    5. Functional simulation.
    6. Code coverage – analyze of design verification efficient.
  4. Synthesis process.
  5. Post-synthesis simulation.
  6. Design implementation and hardware accelerated simulation based on FPGA circuit.
    1. The HES 2.3 DVM user interface.
    2. Design implementation.
    3. Design configuration and setup – preparing for the hardware accelerated simulation process.
    4. Hardware simulation.
    5. Comparison of simulation results.
Tutorial requirements:
  1. Aldec Active-HDL 5.1.
  2. Aldec HES board.
  3. Synthesis tool (Leonardo).
  4. Xilinx Implementation tools.
Comments:
This tutorial will take about 4 hours.
Example of workshop slides: