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Program of 2nd International Workshop on
Discrete-Event System Design, DESDes'04
Dychów near Zielona Gora, September 15÷17, 2004
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Wednesday 15.09.2004
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University of Zielona Gora,
Campus A, Podgórna 50,
building A-2, room 6A
7.00-10.30 - Registration
8.30 and 10.30 - Bus leaving for Dychów
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Pensjonat DYCHÓW
Dychów, tel./fax +48 68 383 53 41
e-mail: dychow@hotel.pl
8.00-11.00 - Registration
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11.30-11.50 Conference opening
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11.50-13.20 Invited session
Chairman: Marian Adamski
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| 11.50-12.10 |
Statechart based embedded systems co-design
Luís Gomes, Anikó Costa
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| 12.10-12.40 |
Current and prospective application domains of FPGAs
Juan José Rodríguez-Andina, Maria J. Moure, Elena Lago
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| 12.40-13.00 |
Randomization of a parallel algorithm for solving undefined systems of linear logical equations
Arkadij Zakrevskij
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| 13.00-13.20 |
A dedicated reconfigurable architecture for implementing Petri nets
Norian Marranghello
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| 13.20-13.40 |
ASIC PHM scheduler implementation
FJ González-Castano, Enrique Soto-Campos, R Asorey-Cacheda, C López-Bravo,
José Farina-Rodríguez, Juan José Rodríguez-Andina
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13.50-14.50 Lunch
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15.00-16.15 High-level system design, session I
Chairman: Norian Marranghello, Alexander Barkalov
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| 15.00-15.15 |
Program model of hierarchical Petri-net
Grzegorz Andrzejewski, Andrei Karatkevich
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| 15.15-15.30 |
From non-autonomous Petri net models to code in embedded systems design
Luís Gomes, Joao Paulo Barros, Rui Pais
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| 15.30-15.45 |
Generation of symbolic functional vector for VHDL specifications verification
Ewa Idzikowska
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| 15.45-16.00 |
Direct implementation of Petri net based model in FPGA
Hana Kubátová
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| 16.00-16.15 |
Research on coding efficiency of wavelet-based IMC-3DEZBC codec
Andrzej Pop³awski, Mariusz Szychiewicz, Wojciech Zaj¹c
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16.15-17.00 Coffee break
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17.00-18.00 High-level system design, session II
Chairman: Hana Kubátová, Luís Gomes
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| 17.00-17.15 |
The SystemC behavioral model of IEEE 802153 MAC protocol - design and profiling
Jerzy Ryman, Daniel Dietterle, Kai Dombrowski, Piotr Bubacz
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| 17.15-17.30 |
The intermediate model for hardware/software microsystems based on Petri nets
Andrzej Stasiak, Zbigniew Skowroñski
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| 17.30-17.45 |
Postprocessing enhancement of image sequences coded by 3D wavelet encoder
Mariusz Szychiewicz, Andrzej Pop³awski, Wojciech Zaj¹c
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| 17.45-18.00 |
A design and verification tool for the parallel systems by an extended Petri net and Java executor
Shin'nosuke Yamaguchi, Katsumi Wasaki, Yasunari Shidama
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18.15-19.45 Special session "Digital design by means of SOpC"
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20.00 Dinner / grill
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Thursday 16.09.2004
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8.00-9.00 Breakfast
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9.00-13.00 Excursion
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13.00-14.00 Lunch
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14.15-15.00 Special session "Verification of FB application design"
Chairman: Alexander Barkalov, Wolfgang Halang
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| 14.15-14.30 |
Test support for FB based application design
Wei Zhang
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| 14.30-14.45 |
Safety profile for UML specifications
Shourog Lu
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| 14.45-15.00 |
Safety execution framework for FB applications
Marek Sniezek
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15.15-16.45 Logic controller design
Chairman: Arkadij Zakrevskij, Hana Kubátová
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| 15.15-15.30 |
Structured design of modular logic controllers
Marian Adamski
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| 15.30-15.45 |
Synthesis of control unit with multiple encoding of the sets of microoperations
Alexander A Barkalov, Arkadiusz Bukowiec
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| 15.45-16.00 |
The real difference between linear and branching temporal logics
Dmitrii I Cheremisinov
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| 16.00-16.15 |
Mapping parallel control algorithms onto programmable logic controller programs
Liudmila D Cheremisinova
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| 16.15-16.30 |
Data flow driven optimization of assertions checkers performance in runtime
Miroslaw Forczek, Katarzyna Hrynkiewicz
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| 16.30-16.45 |
Flow price based vehicle traffic distributed control
T Leþia, A Aºtilean, M Hulea, H Vãlean
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16.45-17.30 Coffee break
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17.30-18.30 Microprocessor and Real-Time systems
Chairman: Enrique Soto-Campos, Marian Adamski
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| 17.30-17.45 |
Design environment for microcode development and debugging with AVR microcontrollers (MICoSS)
Stanislav Korbel, Vlastimil Janes
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| 17.45-18.00 |
Urban driving advisory system based on genetic algoritms
Honoriu Vãlean, Tiberiu Leþia, Adina Aºtilean
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| 18.00-18.15 |
A safety-related programmable electronic system for task-oriented real-time execution
Martin Skambraks
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| 18.15-18.30 |
Remarks on the programming of a bit processor used in a bit-byte CPU of a PLC
Miros³aw Chmiel, Edward Hrynkiewicz, Adam Milik
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20.00 Banquet
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Friday 17.09.2004
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8.00-9.00 Breakfast
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9.00-11.30 Programmable logic
Chairman: Arkadij Zakrevskij, Andrei Karatkevich
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| 9.00-9.15 |
Logic synthesis importance and its place in digital circuits design for cryptography and DSP applications
Tadeusz £uba, Mariusz Rawski, Pawel Tomaszewicz
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| 9.15-9.30 |
Synthesis of compositional microprogram control units with transformation of the numbers of inputs
Alexander A Barkalov, Remigiusz Wiœniewski
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| 9.30-9.45 |
Single-level partitioning support in BOOM-II
Petr Fišer, Hana Kubátová
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| 9.45-10.00 |
Fault simulation technology for SOCs
VI Hahanov, OV Melnikova, IV Pobegenko, AN Parfentiy
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| 10.00-10.15 |
Minimization of the Hamming code generator in self checking circuits
Pavel Kubalik, Petr Fišer, Hana Kubátová
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10.15-10.30 Coffee break
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| 10.30-10.45 |
Multi purpose, low cost, programable PCI interface card
Wojciech Zaj¹c, Sebastian Pawlak
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| 10.45-11.00 |
Experimental research of techniques for logic circuits synthesis in PLA basis
Pyotr Bibilo, Nataly Kirienko
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| 11.00-11.15 |
Synthesis and implementation modulo arithmetic in FPGA
Janusz Jab³oñski, Janusz Biernat
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11.30 Conference closing
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12.00-13.00 Lunch
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13.30 Bus departure to Zielona Góra
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