Wednesday, June 27th, 2001
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10:00 - 10:45 Opening Session
Chairperson – M.Adamski
- Arkadij Zakrevskij, Sequent model for description on digital systems behavior
- Adriano Tavares, Carlos Couto, Estimation of WCET using a little language to describe microcontrollers and DSPs architectures
 
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11:00 - 12:00 Session I a. Petri Net-based Digital Design
Chairpersons – L.Gomes, V.Hahanov
- Enrique Soto, Miguel Pereira, Implementing a petri net specyfication in a FPGA using VHDL
- Murat Uzam, Mutlu Avci, Kürşat Yalçin Digital hardware implementation of Petri net based specifications: direct translation from safe automation Petri nets to circuit elements
- Andrei KaratkevichOn algorithms for decyclisation of oriented graphs
- Werner Erhard, Andreas Reinsch, Torsten SchoberModeling and verification of sequential control paths using Petri nets
 
- 12:15 - 13:15 Session II. System Engineering
Chairpersons – C.Couto, A.Karatkevich
- Sérgio Lopes, Joao Monteiro, Simulation and targeting using OORT
- Vaclav Dvorak, Optimizing sw/hw architecture for parallel embedded systems - a case study
- Sławomir Szostak, Silva Robak, Roman Stryjski, Bogdan Franczyk, UML extensions for modeling real-time and embedded systems
- Grzegorz Hamuda, Wolfgang Halang, Correctness Proof of an operating system kernel for hard real time computing
 
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15:00 - 16:00 Session III a. Integrated Circuits
Chairpersons – V.Dvorak, M.Węgrzyn
- Mariusz Rawski, Tadeusz Łuba, Zbigniew Jachna, Rafał Rzechowski, Functional decomposition – the value and implication for modern digital designing
- Hana Kubatova, Implementation of the FSM into FPGA
- Vladimir I. Hahanov, Anna V. Babich, Masud M.D. Mehedi, System of digital device test generation for Active-HDL
- Janusz Jabłoński, Pipeline processing for serial realization of basical arithmetical operations
Thursday, June 28th, 2001
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10:00 - 11:00 Session III b. Integrated Circuits
Chairpersons – T.Łuba
- Mirosław Bandzerewicz, Wojciech Sakowski, Włodzimierz Wrona, A systematic development of virtual components compatible to standard ICs (an industrial experience)
- Dariusz Caban, A positional filter synthesis for FPGA implementation
- Maciej Michalczak, Zbigniew Skowroński, Implementation of pipelining mechanism in re-programmable logic structures with VHDL language usage
- Mirosław Chmiel, Edward Hrynkiewicz, Remarks on parallel bit-byte CPU structures of Programmable Logic Controllers
 
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11:15 - 12:15 Session IV. Hardware Modelling
Chairpersons – E.Hrynkiewicz
- Thorsten Hummel, Wolfgang Fengler, Design of embedded control systems using hybrid Petri nets
- Ewa Idzikowska, Petri net models of VHDL control statements
- Mirosław Forczek, CHDL – an approach for hardware design at the system level
- Grzegorz Łabiak, Symbolic state exploration of controllers specified by means of Statecharts
 
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14:00 - 15:00 Session V. Image Recognition
Chairpersons – E.Soto, R.Stryjski
- Raouf Kh. Sadykhov, Aliaksei N. Klimovich, Leonid Podenok, Automatic system for TV raster parameters tuning
- Jaromir Przybyło, Marek Gorgoń, Flexible resource arbiter for heterogenous image processing system
- Raouf Kh. Sadykhov, Maksim E. Vatkin, Algorithm for images processing of integrated circuits on the basis of the “Neocognitron” neural network
- Valery A. Prytkov, Raouf Kh. Sadykhov, Selection of close classes objects using brightness histogram
 
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15:15 - 16:30 Session I b. Petri Net-based Digital Design
Chairpersons – A.Zakrevskij, H.Kubatova
- Luís Gomes, Joao-Paulo Barros, Using hierarchical structuring mechanisms with Petri nets for PLD based system design
- Marian Adamski, A rigorous design methodology for reprogrammable logic controllers
- Shin'nosuke Yamaguchi, Katsumi Wasaki, Yasunari Shidama, Pauline Naomi Kawamoto, Automatic HDL generation for a DES codec for encrypted NFS server based on an extended Petri net
- Piotr Miczulski, State space calculation algorithm of hierarchical Petri nets with application of decision diagrams
- Grzegorz Andrzejewski, Timed Petri nets for software applications
Friday, June 29th, 2001
- 10:00 - 11:00 Panel Session
Chairpersons – E.Dagless, C. Couto
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- 11:15 - 11:45 Poster Session
- Dmitrij Cheremisinov, Deriving programs from parallel algorithms of logical control
- Yury Pottosin, On optimal state-assignment of synchronous parallel automata
- Raouf Kh. Sadykhov, Aliaksei V.Otwagin, Algorithm for optimization of parallel computations on the basis of genetic algorithms and model of a virtual network
- Ljudmila Cheremisinova, State assignment of asynchronous parallel automata
- Pyotr Bibilo, Natalia Kirienko, Block synthesis of combinational circuits in the basis of PLA and library gates
- Agnieszka Węgrzyn, Piotr Bubacz, XML application for modelling and simulation of concurrent controllers
- Miguel Pereira, Enrique Soto, Fail-safe VHDL descriptions of Petri net specifications
- Remigiusz Wiśniewski, Arkadiusz Bukowiec, Marek Węgrzyn, Benefits of hardware accelerated simulation
- Maksim E. Vatkin, Mikhail Selinger, The system of handwritten characters recognition on the basis of legendre moments and neural network
 
- 11:15 - 12:15 Exhibition
- HDL simulation and hardware accelerated simulation tools, ALDEC, Inc.
- The new era of Document Managers: e-STUDIO, Biuro 2000
- Modern multimedia tools in engineer's education - VASCO package, MABEX-Multimedia, Ltd.
Social events:
- June 27, 2001
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16:30 - Excursion to the ethnographical museum Skansen (Ochla)
20:00 - Fire with grilled sausages
- June 28, 2001
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17:00-19:00 - Walking trip (Przytok and neighborhood)
20.00 - Banquette
- June 29, 2001
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13.00 - Picnic in the country
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