Workshop schedule

Wednesday, June 27th, 2001

10:00 - 10:45 Opening Session
   Chairperson – M.Adamski
  1. Arkadij Zakrevskij, Sequent model for description on digital systems behavior
  2. Adriano Tavares, Carlos Couto, Estimation of WCET using a little language to describe microcontrollers and DSPs architectures
 
11:00 - 12:00 Session I a. Petri Net-based Digital Design
   Chairpersons – L.Gomes, V.Hahanov
  1. Enrique Soto, Miguel Pereira, Implementing a petri net specyfication in a FPGA using VHDL
  2. Murat Uzam, Mutlu Avci, Kürşat Yalçin Digital hardware implementation of Petri net based specifications: direct translation from safe automation Petri nets to circuit elements
  3. Andrei KaratkevichOn algorithms for decyclisation of oriented graphs
  4. Werner Erhard, Andreas Reinsch, Torsten SchoberModeling and verification of sequential control paths using Petri nets
 
12:15 - 13:15 Session II. System Engineering
   Chairpersons – C.Couto, A.Karatkevich
  1. Sérgio Lopes, Joao Monteiro, Simulation and targeting using OORT
  2. Vaclav Dvorak, Optimizing sw/hw architecture for parallel embedded systems - a case study
  3. Sławomir Szostak, Silva Robak, Roman Stryjski, Bogdan Franczyk, UML extensions for modeling real-time and embedded systems
  4. Grzegorz Hamuda, Wolfgang Halang, Correctness Proof of an operating system kernel for hard real time computing
 
15:00 - 16:00 Session III a. Integrated Circuits
   Chairpersons – V.Dvorak, M.Węgrzyn
  1. Mariusz Rawski, Tadeusz Łuba, Zbigniew Jachna, Rafał Rzechowski, Functional decomposition – the value and implication for modern digital designing
  2. Hana Kubatova, Implementation of the FSM into FPGA
  3. Vladimir I. Hahanov, Anna V. Babich, Masud M.D. Mehedi, System of digital device test generation for Active-HDL
  4. Janusz Jabłoński, Pipeline processing for serial realization of basical arithmetical operations

Thursday, June 28th, 2001

10:00 - 11:00 Session III b. Integrated Circuits
   Chairpersons – T.Łuba
  1. Mirosław Bandzerewicz, Wojciech Sakowski, Włodzimierz Wrona, A systematic development of virtual components compatible to standard ICs (an industrial experience)
  2. Dariusz Caban, A positional filter synthesis for FPGA implementation
  3. Maciej Michalczak, Zbigniew Skowroński, Implementation of pipelining mechanism in re-programmable logic structures with VHDL language usage
  4. Mirosław Chmiel, Edward Hrynkiewicz, Remarks on parallel bit-byte CPU structures of Programmable Logic Controllers
 
11:15 - 12:15 Session IV. Hardware Modelling
   Chairpersons – E.Hrynkiewicz
  1. Thorsten Hummel, Wolfgang Fengler, Design of embedded control systems using hybrid Petri nets
  2. Ewa Idzikowska, Petri net models of VHDL control statements
  3. Mirosław Forczek, CHDL – an approach for hardware design at the system level
  4. Grzegorz Łabiak, Symbolic state exploration of controllers specified by means of Statecharts
 
14:00 - 15:00 Session V. Image Recognition
   Chairpersons – E.Soto, R.Stryjski
  1. Raouf Kh. Sadykhov, Aliaksei N. Klimovich, Leonid Podenok, Automatic system for TV raster parameters tuning
  2. Jaromir Przybyło, Marek Gorgoń, Flexible resource arbiter for heterogenous image processing system
  3. Raouf Kh. Sadykhov, Maksim E. Vatkin, Algorithm for images processing of integrated circuits on the basis of the “Neocognitron” neural network
  4. Valery A. Prytkov, Raouf Kh. Sadykhov, Selection of close classes objects using brightness histogram
 
15:15 - 16:30 Session I b. Petri Net-based Digital Design
   Chairpersons – A.Zakrevskij, H.Kubatova
  1. Luís Gomes, Joao-Paulo Barros, Using hierarchical structuring mechanisms with Petri nets for PLD based system design
  2. Marian Adamski, A rigorous design methodology for reprogrammable logic controllers
  3. Shin'nosuke Yamaguchi, Katsumi Wasaki, Yasunari Shidama, Pauline Naomi Kawamoto, Automatic HDL generation for a DES codec for encrypted NFS server based on an extended Petri net
  4. Piotr Miczulski, State space calculation algorithm of hierarchical Petri nets with application of decision diagrams
  5. Grzegorz Andrzejewski, Timed Petri nets for software applications

Friday, June 29th, 2001

10:00 - 11:00 Panel Session
   Chairpersons – E.Dagless, C. Couto
 
11:15 - 11:45 Poster Session
  1. Dmitrij Cheremisinov, Deriving programs from parallel algorithms of logical control
  2. Yury Pottosin, On optimal state-assignment of synchronous parallel automata
  3. Raouf Kh. Sadykhov, Aliaksei V.Otwagin, Algorithm for optimization of parallel computations on the basis of genetic algorithms and model of a virtual network
  4. Ljudmila Cheremisinova, State assignment of asynchronous parallel automata
  5. Pyotr Bibilo, Natalia Kirienko, Block synthesis of combinational circuits in the basis of PLA and library gates
  6. Agnieszka Węgrzyn, Piotr Bubacz, XML application for modelling and simulation of concurrent controllers
  7. Miguel Pereira, Enrique Soto, Fail-safe VHDL descriptions of Petri net specifications
  8. Remigiusz Wiśniewski, Arkadiusz Bukowiec, Marek Węgrzyn, Benefits of hardware accelerated simulation
  9. Maksim E. Vatkin, Mikhail Selinger, The system of handwritten characters recognition on the basis of legendre moments and neural network
 
11:15 - 12:15 Exhibition
  1. HDL simulation and hardware accelerated simulation tools, ALDEC, Inc.
  2. The new era of Document Managers: e-STUDIO, Biuro 2000
  3. Modern multimedia tools in engineer's education - VASCO package, MABEX-Multimedia, Ltd.

Social events:

June 27, 2001
16:30 - Excursion to the ethnographical museum Skansen (Ochla)
20:00 - Fire with grilled sausages
June 28, 2001
17:00-19:00 - Walking trip (Przytok and neighborhood)
20.00 - Banquette
June 29, 2001
13.00 - Picnic in the country

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